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low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer ics87931i-147 idt ? / ics ? lvcmos clock multiplier/zero delay buffer 1 ics87931ayi-147 rev. a august 25, 2010 g eneral d escription the ics87931i-147 is a low voltage, low skew lvcmos/lvttl clock multiplier/zero delay buffer. with output frequencies up to 240mhz, the ics87931i is targeted for high performance clock applications. along with a fully integrated pll, the ics87931i-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with ?zero delay?. selectable clock inputs, clk1 and differential clk0, nclk0 support redundant clock applications. the clk_sel input determines which reference clock is used. the output divider values of bank a, b and c are controlled by the div_sela, div_selb and div_selc, respectively. for test and system debug purposes, the pll_sel input al- lows the pll to be bypassed. when low, the nmr input re- sets the internal dividers and forces the outputs to the high impedance state. the effective fanout of the ics87931i-147 can be increased to 12 by utilizing the ability of each output to drive two series terminated transmission lines. f eatures ? fully integrated pll ? six lvcmos/lvttl outputs, 7 typical output impedance ? selectable differential clk0, nclk0 or lvcmos/lvttl clock for redundant clock applications ? maximum output frequency: 240mhz ? vco range: 220mhz to 480mhz ? external feedback for ?zero delay? clock regeneration ? output skew: 165ps (maximum) ? cycle-to-cycle jitter: 45ps (maximum) ? 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages p in a ssignment 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 gnd qb0 qb1 v ddo extfb_sel clk_sel pll_sel nc nc v dda power_dn clk1 nmr clk0 nclk0 gnd gnd qc1 qc0 v ddo ext_fb clk_en1 clk_en0 nc gnd qa1 qa0 v ddo div_sela div_selb div_selc nc ics87931i-147 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view power_dn pll_sel clk_sel clk1 clk0 nclk0 extfb_sel ext_fb div_sela div_selb clk_en0 clk_en1 div_selc nmr qa0 qa1 qb0 qb1 qc0 qc1 pullup pulldown pullup pullup pullup pullup pullup pullup pullup pulldown pulldown pulldown pulldown none 0 1 0 1 1 0 1 0 power-on reset phase detector lpf disable logic vco 8 4/6 2/4 2/4 2 b lock d iagram
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 2 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 2 3 , 7 1 , 9 , 1c nd e s u n u. t c e n n o c o n 2v a d d r e w o p. n i p y l p p u s g o l a n a 3n d _ r e w o pt u p n ip u l l u p . s r e d i v i d t u p t u o e h t o t d e f g n i e b y c n e u q e r f e h t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 41 k l ct u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c 5r m nt u p n ip u l l u p e r a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . t e s e r r e t s a m w o l e v i t c a l a n r e t n i e h t , h g i h c i g o l n e h w . w o l o g o t s t u p t u o e h t g n i s u a c t e s e r . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d 60 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 70 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 5 2 , 4 2 , 6 1 , 8d n gr e w o p. d n u o r g y l p p u s r e w o p 1 1 , 0 1 , 0 n e _ k l c 1 n e _ k l c t u p n ip u l l u p . b 3 e l b a t e e s . s t u p t u o k c o l c e h t f o g n i l b a s i d d n a g n i l b a n e e h t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 1b f _ t x et u p n ip u l l u p . k c a b d e e f l a n r e t n i s t c e l e s , w o l n e h w . k c a b d e e f l a n r e t x e . s l e v e l e c a f r e t n i l t t v l / s o m c v l . b f _ t x e s t c e l e s , h g i h n e h w 8 2 , 1 2 , 3 1v o d d r e w o p. s n i p y l p p u s t u p t u o 5 1 , 4 11 c q , 0 c qt u p t u o 7 . s t u p t u o k c o l c c k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8 1l e s _ l l pt u p n ip u l l u p e h t o t t u p n i e h t s a s k c o l c e c n e r e f e r d n a l l p e h t n e e w t e b s t c e l e s s e s s a p y b , w o l n e h w . l l p s t c e l e s , h g i h n e h w . s r e d i v i d t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . l l p e h t 9 1l e s _ k l ct u p n in w o d l l u p . e c n e r e f e r r o t c e t e d e s a h p e h t s t c e l e s . t u p n i t c e l e s k c o l c . 1 k l c s t c e l e s , h g i h n e h w . 0 k l c n , 0 k l c s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 2l e s _ b f t x et u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t c e l e s k c a b d e e f l a n r e t x e 3 2 , 2 20 b q , 1 b qt u p t u o 7 . s t u p t u o k c o l c b k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 2 , 6 20 a q , 1 a qt u p t u o 7 . s t u p t u o k c o l c a k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 9 2a l e s _ v i dt u p n in w o d l l u p . a 4 e l b a t n i d e b i r c s e d s a a k n a b r o f s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 3b l e s _ v i dt u p n in w o d l l u p . a 4 e l b a t n i d e b i r c s e d s a b k n a b r o f s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 3c l e s _ v i dt u p n in w o d l l u p . a 4 e l b a t n i d e b i r c s e d s a c k n a b r o f s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v , o d d v o d d v 5 6 4 . 3 =2 1f p r t u o e c n a d e p m i t u p t u o 7
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 3 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer t able 3b. clk_en x f unction t able t able 4a. vco f requency f unction t able s t u p n in o i t c n u f n i p l o r t n o c0 c i g o l1 c i g o l l e s _ k l c0 k l c n , 0 k l c1 k l c l e s _ l l pl l p s s a p y bd e l b a n e l l p l e s _ b f t x ek c a b d e e f l a n r e t n ib f _ t x e n d _ r e w o p1 / o c v2 / o c v r m nz i h t u p t u o / t e s e r r e t s a ms t u p t u o e l b a n e c l e s _ v i d : a l e s _ v i d) 4 ( c q ; ) 2 ( b q ; ) 2 ( a q) 6 ( c q ; ) 4 ( b q ; ) 4 ( a q t able 3a. c ontrol i nput f unction t able t able 4b. i nput r eference f requency to o utput f requency f unction t able (i nternal f eedback o nly , extfb_sel = 0) s t u p n is t u p t u o _ v i d a l e s _ v i d b l e s _ v i d c l e s x a qx b qx c q 0 = n d _ r e w o p1 = n d _ r e w o p0 = n d _ r e w o p1 = n d _ r e w o p0 = n d _ r e w o p1 = n d _ r e w o p 000 2 / o c v4 / o c v2 / o c v4 / o c v4 / o c v8 / o c v 00 1 2 / o c v4 / o c v2 / o c v4 / o c v6 / o c v2 1 / o c v 010 2 / o c v4 / o c v4 / o c v8 / o c v4 / o c v8 / o c v 011 2 / o c v4 / o c v4 / o c v8 / o c v6 / o c v2 1 / o c v 10 0 4 / o c v8 / o c v2 / o c v4 / o c v4 / o c v8 / o c v 10 1 4 / o c v8 / o c v2 / o c v4 / o c v6 / o c v2 1 / o c v 110 4 / o c v8 / o c v4 / o c v8 / o c v4 / o c v8 / o c v 111 4 / o c v8 / o c v4 / o c v8 / o c v6 / o c v2 1 / o c v s t u p n is t u p t u o _ v i d a l e s _ v i d b l e s _ v i d c l e s x a qx b qx c q 0 = n d _ r e w o p1 = n d _ r e w o p0 = n d _ r e w o p1 = n d _ r e w o p0 = n d _ r e w o p1 = n d _ r e w o p 000 x 4x 2x 4x 2x 2x 00 1 x 4x 2x 4x 2x 3 / 4x 3 / 2 010 x 4x 2x 2xx 2x 011 x 4x 2x 2x x 3 / 4x 3 / 2 10 0 x 2xx 4x 2x 2x 10 1 x 2xx 4x 2x 3 / 4x 3 / 2 110 x 2xx 2xx 2x 111 x 2xx 2x x 3 / 4x 3 / 2 s t u p n i 1 n e _ k l c0 n e _ k l c c l e s v i d : a l e s _ v i d x a qx b qx c q 00 e l g g o tw o lw o l 01 w o lw o le l g g o t 10 e l g g o tw o le l g g o t 11 e l g g o te l g g o te l g g o t
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 4 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer vco vco/2 power_dn qa(2) qb(4) qc(6) qa qb qc clk_en0 clk_en1 qa(2) qb(4) qc(6) clk_en0 clk_en1 f igure 1a. power_dn t iming d iagram f igure 1b. clk_en x t iming d iagrams
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 5 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i n i t n e r r u c t u p n i 0 2 1 a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv o d d 5 8 . 0 -v s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n , v s i 0 k l c n , 0 k l c r o f e g a t l o v t u p n i m u m i x a m e h t o d d . v 3 . 0 + s i e g a t l o v e d o m n o m m o c : 2 e t o nv s a d e n i f e d h i . t able 5c. d ifferential dc c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c t able 5b. lvcmos/lvttl dc c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c t able 5a. p ower s upply dc c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i a d d t n e r r u c y l p p u s g o l a n a 0 2a m i o d d t n e r r u c y l p p u s t u p t u o 0 0 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n i e g a t l o v h g i h , c l e s _ v i d : a l e s _ v i d , 0 n e _ k l cn e _ k l c, 1 n , n d _ r e w o p, l e s _ k l c , r m , l e s _ b f t x e , l e s _ l l p b f _ t x e , 1 k l c 2v o d d 3 . 0 +v v l i t u p n i e g a t l o v w o l , c l e s _ v i d : a l e s _ v i d , 1 n e _ k l c , 0 n e _ k l c , l e s _ k l c , r m n , n d _ r e w o p l e s _ b f t x e , l e s _ l l p 3 . 0 -8 . 0v b f _ t x e , 1 k l c3 . 0 -3 . 1v i n i t n e r r u c t u p n i 0 2 1 a v h o 1 e t o n ; e g a t l o v h g i h t u p t u oi h o a m 0 2 - =4 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u oi l o a m 0 2 =5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o d d . t i u c r i c t s e t d a o l t u p t u o v 3 . 3 , n o i t c e s t n e m e r u s a e m r e t e m a r a p e e s . 2 / a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dda + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 65.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability.
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 6 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer t able 6. pll i nput r eference c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f f e r y c n e u q e r f e c n e r e f e r t u p n i y b d e t i m i l s i y c n e u q e r f e c n e r e f e r t u p n i : e t o n . e g n a r k c o l o c v e h t d n a n o i t c e l e s r e d i v i d e h t 0 4 2z h m t able 7. ac c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o x b q , x a q2 0 4 2z h m x c q , x b q , x a q4 0 2 1z h m x c q6 0 8z h m ) ? ( t ; t e s f f o e s a h p c i t a t s 1 e t o n b f _ t x e o t 1 k l c , z h m 0 5 = f e r f 8 = b f 5 7 3 -0 0 2 -0 5 -s p b f _ t x e o t 0 k l c n , 0 k l c0 0 1 -0 50 0 2s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 5 6 1s p t ) c c ( r e t t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y c 5 4s p f o c v e g n a r k c o l o c v l l p 0 2 20 8 4z h m t r t / f 3 e t o n ; e m i t e s i r t u p t u ov 0 . 2 o t v 8 . 01 . 01s n c d oe l c y c y t u d t u p t u of x a m z h m 0 5 1 <5 45 5% t k c o l e m i t k c o l l l p 0 1s m t l z p t , h z p ; e m i t e l b a n e t u p t u o3 e t o n20 1s n t z l p ,t z h p ; e m i t e l b a s i d t u p t u o3 e t o n28s n t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u e h t n e h w l a n g i s t u p n i k c a b d e e f e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 1 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m o d d . 2 / . n o i t c u d o r p n i d e t s e t t o n . n o i t a z i r e t c a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h t : 3 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 7 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer qax, qbx, qcx t period t pw t period odc = v ddo 2 x 100% t pw p arameter m easurement i nformation o utput s kew d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx lvcmos gnd 1.65v5% gnd = -1.165v5% qax, qbx, qcx ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles s tatic p hase o ffset t cycle n t cycle n+1 o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod t sk(o) v ddo 2 v ddo 2 qy qx v dda 2 v ddo 2 clk1 ext_fb clock outputs 0.8v 2v 2v 0.8v t r t f nclk0 clk0 v cmr cross points v pp nclk0 clk0 gnd v dd c ycle - to -c ycle j itter v dda, v ddo
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 8 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd i nputs : clk i nput : for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utputs : all unused lvcmos output can be left floating. there should be no trace attached.
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 9 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. the signals must meet the v pp and v cmr input requirements. figures 3a to 3d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please f igure 3a. clk/nclk i nput d riven by an idt lvhstl d river consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for idt lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3c. clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 3b. clk/nclk i nput d riven by a 3.3v lvpecl d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v f igure 3d. clk/nclk i nput d riven by a 3.3v lvds d river zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 10 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer f igure 4a. ics87931i-147 s chematic e xample s chematic e xample figure 4a shows a schematic example of using an ics87931i- 147. it is recommended to have one decouple capacitor per power pin. each decoupling capacitor should be located as close as possible to the power pin. the low pass filter r7, c11 and c16 for clean analog supply should also be located as close to the v dda pin as possible. vdd=3.3v r4 1k c2 0.1uf r2 43 vdd set logic input to '1' to logic input pins r3 1k power_dn set logic input to '0' c16 10u zo = 50 ohm r8 50 ru2 not install zo = 50 c11 0.01u div_selb vdd clk_en0 receiv er vdd r9 50 div_selc r1 43 r10 50 to logic input pins r7 10 - 15 (u1-28) rd2 1k vdd receiv er vdd vdd u1 ics87931i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 nc vdda power_dn clk1 nmr clk0 nclk0 gnd nc clk_en0 clk_en1 ext_fb vddo qc0 qc1 gnd nc pll_sel clk_sel extfb_sel vddo qb1 qb0 gnd nc div_selc div_selb div_sela vddo qa0 qa1 gnd logic input pin examples ru1 1k (u1-13) c3 0.1uf zo = 50 ohm div_sela rd1 not install zo = 50 3.3v pecl driv er clk_en1 r5 1k sp = space (i.e. not intstalled) c1 0.1uf 3.3v (u1-21) ics87931i-147
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 11 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer f igure 4b. pcb b oard l ayout f or ics87931i-147 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors as close as possible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v dda pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the differential 50 output traces should have same length. ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock traces on the same layer. whenever pos- sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. ? make sure no other signal traces are routed between the clock trace pair. ? the series termination resistors should be located as close to the driver pins as possible. c2 pin 1 c11 u1 gnd 50 ohm trace vcca other signals c3 via r1 c16 vcc c1 r7 r2 50 ohm trace
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 12 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer r eliability i nformation t ransistor c ount the transistor count for ics87931i-147 is: 2942 t able 8. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (meters per second) 0 1.0 2.5 multi-layer pcb, jedec standard test boards 65.7c/w 55.9c/w 52.4c/w
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 13 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer t able 9. p ackage d imensions reference document: jedec publication 95, ms-026 p ackage o utline - y s uffix for 32 l ead lqfp n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 14 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 7 4 1 - i y a 1 3 9 7 87 4 1 i a 1 3 9 7 s c ip f q l d a e l 2 3y a r tc 5 8 o t c 0 4 - t 7 4 1 - i y a 1 3 9 7 87 4 1 i a 1 3 9 7 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l 7 4 1 - i y a 1 3 9 7 8l 7 4 1 i a 1 3 9 s c ip f q l " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l 7 4 1 - i y a 1 3 9 7 8l 7 4 1 i a 1 3 9 s c ip f q l " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? lvcmos clock multiplier/zero delay buffer 15 ics87931ayi-147 rev. a august 25, 2010 ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d ab 4 t3 n o i t p i r c s e d e l b a t o t d e d d a - e l b a t y c n e u q e r f e c n e r e f e r t u p n i . " 0 = l e s _ b f t x e " 0 1 / 5 2 / 8
ics87931i-147 low skew, 1-to-6 lvcmos/lvttl clock multiplier/zero delay buffer we?ve got your timing solution. sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt tech support netcom@idt.com +480-763-2056 6024 silver creek valley road san jose, ca 95138 ? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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